1. Technical Field
The present invention relates to a semiconductor device, and in particular to a structure of semiconductor package.
2. Related Art
System-in-package (SiP, hereinafter) technology, realizing a plurality of functions such as memory, CPU (central processing unit) and so forth in a single package, has been attracting public attention as a semiconductor packaging technology expected as realizing more advanced functions and thinning of semiconductor devices. Package-on-package (PoP, hereinafter) technology is one known SiP technology, characterized by stacking of a plurality of semiconductor packages in a three-dimensional manner. PoP allows arbitrary selection of combination of a plurality of functions, as being adapted to applications. It can reduce the effective area, by virtue of its structure in which the semiconductor packages are stacked in a three-dimensional manner. It is, therefore, adoptable mainly to small-sized, thin, and multi-functional instruments such as mobile phones.
An exemplary sectional structure related to the conventional PoP technology is shown in FIG. 28. A first package 100 disposed on the lower stage has a wiring board 101 and a semiconductor chip 12 bonded thereon by the flip-chip bonding process, wherein an underfill resin 13 is filled between the wiring board 101 and the semiconductor chip 12. The semiconductor chip 12 and the wiring board 101 are connected through bumps 19 composed of gold, solder, or the like. On the back surface of the wiring board 101, solder balls 17 are formed as external connection terminals. It is to be understood that the drawing is a schematic one, wherein the first semiconductor package 100 in practice generally causes some warping as described later.
A second semiconductor package 200 disposed on the upper stage is configured by stacking two semiconductor chips 12 stacked on the wiring board 101, wherein the wiring board 101 and the semiconductor chips 12 are bonded by the wire bonding process through wires 14, and are molded by a molding resin 15. The semiconductor chips 12 and the wiring board 101, or two semiconductor chip 12 are stacked while placing a chip mounting adhesive 16. The first semiconductor package 100 and the second semiconductor package 200 are bonded through the solder balls 17, and are thereby configured as a PoP.
FIGS. 29A and 29B and FIGS. 30A and 30B show the first semiconductor packages. FIGS. 29A and 29B show a configuration having the semiconductor chip 12 and the board 11 connected by wire bonding through wires 14, and FIGS. 30A and 30B show a configuration based on the flip-chip bonding process. In the individual drawings, figures A and B are plan views and sectional views taken along line A-A′, respectively. It is not always necessary for the first semiconductor package in the flip-chip bonding that the semiconductor chip is covered with the molding resin, but a portion at and around the semiconductor chip 12 may be covered with the molding resin 15, as shown in FIG. 30.
In this sort of PoP, suppression of warping of the first semiconductor package 100 may be one problem to be solved. The warping is mainly ascribable to difference in coefficient of thermal expansion between the board and the semiconductor chip. As described later, the warping of the first semiconductor package 100 may result in bonding failure at portions of bonding with the second semiconductor package 200 stacked thereon.
Technical literatures relevant to suppression of semiconductor packages may be exemplified by Japanese Laid-Open Patent Publication Nos. H08-162573 and H10-022422.
Japanese Laid-Open Patent Publication No. H08-162573 discloses a technique of suppressing floating of wires or warping of a semiconductor package formed by wire bonding, by molding a semiconductor chip using a double-layered resin composed of an inner cured resin layer and an outer cured resin layer. Use of a resin suppressive to wire floating may increase warping of the package, so that the wire portion is first molded using the resin suppressive to wire floating, and the outer circumference is then molded using a resin suppressive to warping.
Japanese Laid-Open Patent Publication No. H10-022422 discloses a technology of preventing cracks in the package, by configuring the molding resin of semiconductor chips using a low-stress inner resin layer and a low-hygroscopic outer resin layer.
As described in the above, warping of the first semiconductor package is exemplified as one critical issue in the PoP technology.
FIGS. 31A to 31C are sectional view schematically showing warping behaviors of the first semiconductor packages. FIG. 31A shows a case where wire bonding was adopted as a method of bonding a semiconductor chip, and FIGS. 31B and 31C show cases where the flip-chip bonding was adopted. FIGS. 31A and 31B show cases where the semiconductor chip 12 was covered with the molding resin 15, and FIG. 31C shows a case where the molding resin was not used. Irrespective of the structures, the first semiconductor packages warp to the upper side (semiconductor chip side) of the board 11 under normal temperature so as to cause convex warping (cry warping, hereinafter), and warp to the-lower side (solder ball side) of the board 11 under fusing temperature of solder so as to cause concave warping (smile warping, hereinafter). Although not so clear in the drawings, also the molding resin 15 warps conforming to warping of the board 11 and the semiconductor chip 12.
FIGS. 32A to 32C are schematic sectional views of a PoP structure using the first semiconductor package shown in FIGS. 31A to 31C. The first semiconductor packages 100 shown in FIGS. 32A to 32C have the same configurations with those shown in FIGS. 31A to 31C, respectively. The second semiconductor package 200 has the same configuration with that shown in FIG. 28. The drawings show states of bonding when the first semiconductor package 100 and the second semiconductor package 200 are bonded, that is, the states of bonding under fusing temperature of solder. Because the first semiconductor package 100 causes the smile warping, unbonded portions 20 appear between the first semiconductor package 100 and the solder balls 17 on the second semiconductor package 200. Although not so clear in the drawings, also the molding resin 15 of the first semiconductor package 100 warps conforming to warping of the board 11 and the semiconductor chip 12.
As described in the above, large warping under fusing temperature of solder may result in bonding failure between the first semiconductor package 100 and the second semiconductor package 200. Even if the bonding failure should not occur, bondability may degrade due to temperature cycle in the succeeding processes of manufacturing, making it difficult to obtain a sufficient reliability of bonding.
In addition, thinning and faster speed of communication more than ever are required for recent semiconductor devices. It may, therefore, be necessary to thin the board in the PoP structure than ever, but thinning may reduce the rigidity, because rigidity of the board depends on the thickness, so that the warping of the package may increase more than ever.
Moreover, in view of increasing communication speed, the semiconductor chip is preferably bonded to the board by the flip-chip bonding process. This is because, in the flip-chip bonding process, the board and the circuit plane of the semiconductor chip are directly bonded without using wires therebetween. However, the flip-chip bonding process generally requires process temperatures higher than that of wire bonding, so that amount of change in temperature away from normal temperature may become larger, and the warping may become more distinctive.
As described in the above, efforts of satisfying recent requirements of thinning and speedup of semiconductor device have increased the amount of warping of the semiconductor package than ever. In view of solving this problem and of providing a semiconductor device excellent in the bonding reliability, only a limited effect may be attainable simply by adopting the packaging technologies disclosed in the Patent Publications described in the above, raising a need of further improvement.